`include "timescale.v"

module tb_counter;
   
   reg 			  rst;
   reg 			  clk;
   wire [7:0] 	  count;

   always #5 clk = ~clk;   
   initial
	 begin
		rst = 1; 
		clk = 0;
		#20 rst = 0;
	 end
   
   counter #(
	     .WIDTH(8)
	     ) mycounter (
			  .rst(rst),
			  .clk(clk),
			  .count		(count));


   always@(posedge clk)
	 $display("%t : counter = %x", $time, count);

   initial 
	 #100 $finish;
	 
endmodule // test

